Error Detection
The error detection method is performed by a 16-bit CRC on each signal unit. These 16 bits are called check bits (CK bits).
NOTE
The process uses the Recommendation V.41 [ITU-T Recommendation V.41: CODE-INDEPENDENT ERROR-CONTROL SYSTEM, November 1988] generator polynomial X16 + X12 + X5 + 1. The transmitter's 16-bit remainder value is initialized to all 1s before a signal unit is transmitted. The transmission's binary value is multiplied by X16 and then divided by the generator polynomial. Integer quotient values are ignored, and the transmitter sends the complement of the resulting remainder value, high-order bit first, as the CRC field. At the receiver, the initial remainder is preset to all 1s, and the same process is applied to the serial incoming bits. In the absence of transmission errors, the final remainder is 1111000010111000 (X0 + X15).
The polynomial that is used is optimized to detect error bursts. The check bits are calculated using all fields between the flags and ignoring any inserted 0s. The SP then appends the calculation to the SU before transmission as a two-octet field (CK field). The receiving SP performs the same calculation in an identical manner. Finally, the two results are compared; if an inconsistency exists, the SU is discarded, and the error is noted by adding to the Signal Unit Error Rate Monitor (SUERM). In this case, the error correction procedure is applied.
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