Processor Outage

The processor outage condition occurs when SUs cannot be transferred to MTP3 or above. This could be the result of a central processing failure or communication loss between MTP2 and Levels 3/4 when a distributed processing architecture is used. A processor outage condition won't necessarily affect all signaling links in an SP, nor does it exclude the possibility that MTP3 can control the operation of the signaling link. When MTP2 recognizes a local processor outage condition, it transmits LSSUs with the status field set to status indication processor outage (SIPO) and discards any MSUs it has received. When the distant SP receives the SIPO status LSSU, it notifies its MTP3 and begins to continuously transmit FISUs. Note that the affected links remain in the aligned state.